The present invention relates in general to a method for scheduling the running of layout design verification programs (jobs) for a Very Large Scale Integration (VLSI) chip design.
In the following, several VLSI layout design programs will be discussed. The detailed specific nature of all these program is not necessary to understand the environment for the present invention. These programs may be referred to as simply xe2x80x9cjobsxe2x80x9d in this Specification.
In order to understand the following description, it is useful to review the present VLSI design job environment. The following is a legend of some VLSI layout programs that are used in embodiments of the present invention:
DRCxe2x80x94is a design rules checking program
LVSxe2x80x94is a checking program for Layout versus the Schematic
Yieldxe2x80x94is a program that predicts yields based on a layout
Powerxe2x80x94is a power analysis program
Pathmillxe2x80x94is a vendor transistor level static timing program
Einschkxe2x80x94is a circuit checking program
EinTLTxe2x80x94is a transistor level timing program
Harmonyxe2x80x94is a noise analysis tool
Noise Dracula LPE/PRExe2x80x94parasitic extraction tools that analyze the layout data and create noise (cross coupled capacitance) Spice netlists
Timing Dracula LPE/PRExe2x80x94parasitic extraction tools that analyze layout data and create timing (resistance and capacitance) Spice netlists
Boundary Checkxe2x80x94is a design rules checking program between macros
Create Abstractxe2x80x94creates physical representation of design
Create Blockagexe2x80x94checks if the Abstract is still valid
After a VLSI layout is completed, the designer may need to determine that the layout macro passes various verification programs (e.g., LVS, DRC, and Boundary Check) before extraction programs are run to generate timing/noise net lists. The expected yield of the VLSI chip, represented by the layout, may also be checked at this stage by running a Yield program.
Normally, the VLSI layout designer discretely and manually submits these jobs in series or parallel. FIG. 4 is a flow diagram where these four jobs are submitted in a series mode. The designer completes one job before going to another job. For example, after the designer completes the VLSI layout in step 401, the LVS program is executed in step 402. A test is done in step 403 to determine if LVS has errors. If the result of the test in step 403 is YES, then the errors are fixed in step 413 by the designer and the LVS program is run again by branching to step 402. If the result of the test in step 403 is NO, then the next program, DRC, is run in step 404. A test is done in step 405 to determine if DRC has errors. If the result of the test in step 405 is YES, then the errors are fixed by the designer and a branch is made to a test in step 414 to determine if only some of the program set are to be rerun. If the test in step 414 is NO, then step 402 runs the program set from the beginning. If the result in step 414 is YES, then the program set starts at the DRC program in step 404. If the result of the test in step 405 is NO, then the Integration program is run in step 406. A test is done in step 408 to determine if the Integration program has errors. If the result of the test in step 408 is YES, then the errors are fixed in step 411 and then in step 415 a test is run to determine if only some of the programs are to be rerun. If the result in step is NO, then step 414 executes the test as described earlier. If the result in step 415 is YES, then the program set is rerun starting at the program Integration in step 406. If the result of the test in step 408 is NO, then the Yield program is run in step 409. A test is then run in step 410 to determine if the Yield program had any errors. If the result of the test in step 410 is YES, then the errors are fixed in step 412 and then a test is run in step 416 to determine if only the Yield program is to be rerun. If the result of the test in step 416 is NO, then the tests in steps 415 and 414 are run as explained earlier. If the result of the test in step 416 is YES, then the program set is rerun starting at the Yield program. If the result of the test in step 410 is NO, then the execution of layout programs may branch to a noise model extraction program (e.g., Noise Dracula LPE/PRE) in step 417.
In a parallel program execution mode, the designer submits the exemplary four layout design jobs (e.g., DRC, LVS, Integration and Yield are executed concurrently) in parallel. If any one of the jobs fails, the designer has two options. The first option is to cancel the remaining incomplete jobs so the designer may fix the problems associated with one design program at a time. A second option is to let the remaining uncompleted jobs run to completion. The designer then may analyze the results of the completed jobs and attempt to fix errors in all the jobs at the same time. In either option, the process repeats itself until all jobs are error free.
Either in series or parallel mode, the designer has to discretely and manually submit and cancel the jobs. In order to do so, the designer needs to keep track of all of the jobs submitted. For example, after DRC, LVS, Boundary Check, and Yield programs are error free, the next step is to generate the timing/noise net lists. In order to accurately account for the global wiring over the macro, an Abstract that is consistent with the macro wiring is created. An extraction program uses the created Abstract to form a possible global wiring over the macro. The macro is then extracted with that global wiring. One can see that before an extraction is run, either an Abstract already exists or if the Abstract is present it must reflect an associated macro wiring.
In the prior art, submitting the VLSI design jobs is very much a sequential, step-by-step, and manual process, where the process flow is directed by an individual designer. There is, therefore, a need for a method to automatically submit VLSI design jobs to simplify the designer""s task and allow VLSI design and verification to proceed more quickly.
The VLSI layout design task comprises a set of design programs or jobs that are run on data created by a designer. To streamline the VLSI design and verification process, the necessary or desired design programs are organized like machine states which are interconnected with a program (job) scheduler. The different programs become program states within the design process with different criteria determining transitions between the program states. The different programs have program data inputs and program output data, either from an initial database or from other programs in the process flow. Programs also have program logic outputs and inputs which may indicate if the programs have completed error free, completed conditionally, or have output data that is conditionally or unconditionally valid. Other logic routine states are created within the scheduler wherein the program logic outputs from the programs are used to determine additional logic routine outputs which in turn are used to launch, cancel, or otherwise modify programs within the process. When the design process is initiated, a set of programs may run until the first program, which fails or becomes interrupted because of errors, stops or interrupts other incomplete programs. The designer then may correct the errors of the first failed program. The designer restarts the design process and the scheduler begins in the suspended state generating new outputs for the interrupted first program and other previously incomplete programs. Embodiments of the invention may complete programs with conditional inputs to complete a design pass and create a database that is known to have errors. The transitions between the program and logic routine states are rule based and take paths dependent on designer input for designer controls and program and logic routine outputs. However, the designer does not have to keep track of which programs have been submitted. Rather, the designer corrects errors in one or multiple programs as desired and enters new data and the program execution is controlled by the scheduler. The designer may start the design process under various operational modes. These operational modes, such as Audit Mode, Non Audit Mode and Edit Mode, may alter conditions that determine transitions between the program states.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.